1. Field of the Invention
The present invention relates to an oscillating circuit that generates oscillating signals using inverting circuits cascaded in the form of a ring, and particularly to an oscillating circuit that can control oscillation frequency.
2. Description of the Related Art
PLL (phase-locked loop) circuits are widely used to generate an oscillating signal with a high spectral accuracy or generate a clock signal locked in frequency and phase to a data signal. Examples of applications of the PLL circuit include radio communications of portable telephones and the like, serial communications through various cables, and reproducing systems (read channels) for reproducing digital recorded data on disk media.
A first performance requirement for the PLL circuit is the precision of an output signal. Because the precision of the output signal is decreased by thermal noise and various noises inherent in elements, this decrease is desired to be prevented. In general, jitter performance and phase noise are widely used as an index for evaluating the precision.
A PLL circuit includes a voltage controlled oscillating circuit (voltage controlled oscillator, which will hereinafter be described as a VCO). In many cases, this VCO is a main factor in jitter and phase noise. A method of improving jitter performance by PLL band adjustment is a method of reducing noise by correction, whereas improving the jitter performance of the VCO corresponds to reduction of noise itself.
There are two kinds of VCO configurations capable of being integrated, that is, an LCVCO using a resonant circuit of an inductor and a capacitor, and a ring VCO. In general, the LCVCO excels the ring VCO in jitter performance. On the other hand, the ring VCO has advantages of having a wide frequency variable range, being able to output a plurality of output signals different from each other in phase, and not requiring an inductor, for example. Therefore the ring VCO is widely used in applications where a jitter performance requirement is not so stringent. Eliminating the need for an inductor, in particular, can not only greatly alleviate a disadvantage of generating an undesired electromagnetic field and thereby affecting other circuits, but also provide a great advantage in terms of cost because circuit area can be reduced greatly. For the above reasons, improvements of jitter and phase noise performance of the ring VCO are strongly desired.
FIG. 16 is a diagram showing an example of configuration of an ordinary ring VCO.
The ring VCO is generally formed by cascading a plurality of VCO cells equivalent to each other in the form of a ring.
The oscillation frequency fo of the ring VCO can be expressed by the following equation with the delay time Td of the VCO cells and the number N of stages of the VCO cells.
[Equation 1]fo=1/(2·N·Td)  (1)
The output signals of adjacent VCO cells have a phase difference of 2π/N [rad].
The ring VCO is broadly divided into two types, that is, a differential type and a single-ended type.
FIG. 17 is a diagram showing an example of configuration of a cell in an ordinary single-ended VCO.
The VCO cell shown in FIG. 17 has a CMOS structure in which an n-type MOS transistor 501 and a p-type MOS transistor 502 are connected in series with each other, and has variable loads 503 and 504 provided on a ground side and a power supply side, respectively, of the CMOS structure. The CMOS structure shown in FIG. 17 may be replaced with a single-stage amplifier formed by one of the transistors. In addition, one of the two variable loads may be provided. When the number of cell stages in the single-ended VCO is an even number, the output signals of adjacent cells are stable in terms of direct current in a state of being alternately at a high level and a low level (latch). Therefore, to operate the single-ended VCO as an oscillating circuit, the number N of cell stages has to be an odd number.
FIG. 18 shows an example of configuration of an ordinary differential VCO cell.
The VCO cell shown in FIG. 18 has n-type MOS transistors 601 and 602 having sources connected to a common node, a current source circuit 605 for holding constant a current flowing from the common source to a ground GND, and loads 603 and 604 connected between a power supply voltage VDD and the drains of the MOS transistors 601 and 602. Differential signals are input to the gates of the MOS transistors 601 and 602, and differential signals inverted in phase are output from the drains of the MOS transistors 601 and 602.
Recent studies have shown that (under a condition of a same current consumption) the single-ended VCO generally excels the differential VCO in jitter and phase noise performance (see “Jitter and Phase Noise in Ring Oscillators”, IEEE Journal of Solid-State Circuits, USA, June 1999, vol. 34, pp. 790 to 804 referred to as Non-Patent Document 1 hereinafter and “Oscillator Phase Noise: A Tutorial”, IEEE Journal of Solid-State Circuits, USA, March 2000, vol. 35, pp. 326 to 336 referred to as Non-Patent Document 2 hereinafter). However, the single-ended VCO has a few disadvantages.
The first disadvantage is high sensitivity to power supply voltage. When the power supply voltage is varied or the power supply voltage includes noise, characteristics of the single-ended VCO vary greatly, and the jitter and phase noise performance of the single-ended VCO is degraded greatly.
The second disadvantage is the inability of the single-ended VCO to output orthogonal signals. As described above, the single-ended VCO is basically formed by an odd number of stages. Although there are a very large number of systems that may require orthogonal signals (signals having a phase difference of 90°) typified by IQ signals in radio communications, the single-ended type may not generate signals with a phase difference of 90° because of the odd number of stages thereof.
The third disadvantage is a single-ended signal, which tends to be affected by noise from other circuits on a same chip and, at the same time, tends to cause noise affecting these circuits.
The fourth disadvantage is a narrow frequency variable range in general, because the single-ended VCO controls resistance or capacitance, whereas the differential VCO controls total current.
On the other hand, the differential VCO does not have the four disadvantages described above, but is inferior in jitter and phase noise performance to the single-ended VCO. There are a plurality of reasons for this.
First, the differential VCO has small oscillation amplitude. This is because the lowest voltage of the amplitude is limited by the presence of the current source circuit.
Second, while the single-ended VCO can have a symmetric structure with respect to a power supply line and a ground line, this symmetry is generally lost in the differential VCO. This reduces the symmetry of a rising edge and a falling edge of an oscillation waveform, and degrades jitter and phase noise performance. It is known that the reduction in such symmetry has an adverse effect on flicker noise.
Third, in an ordinary differential-pair structure, the voltage of a tail node (N601 in FIG. 18) oscillates at a frequency twice the oscillation frequency. This oscillation distorts the oscillation waveform, and further impairs the symmetry and amplitude, thus constituting a factor in degrading the jitter and phase noise performance.
As described above, the single-ended ring VCO and the differential ring VCO have different advantages and different disadvantages. Various studies in the past have been conducted to realize a configuration that combines the above advantages (see “A Three-Stage Coupled Ring Oscillator with Quadrature Outputs” (IEEE ISCAS. 2001, USA, March 2001, vol. 1, pp. 6 to 9) referred to as Non-Patent Document 3 hereinafter, “A Coupled Two-Stage Ring Oscillator” (IEEE MWSCAS. 2001, USA, August 2001, vol. 2, pp. 878 to 881) referred to as Non-Patent Document 4 hereinafter, “A 900 MHz CMOS Low-Phase-Noise Voltage-Controlled Ring Oscillator With Wide Tuning Range” (IEEE Circuits and Systems II, USA, February 2001, vol. 48, pp. 216 to 221) referred to as Non-Patent Document 5 hereinafter, “A Novel Low Phase Noise 1.8V 900 MHz CMOS Voltage Controlled Ring Oscillator” (IEEE ISCAS. 2003, USA, May 2003, vol. 3, pp. 160 to 163) referred to as Non-Patent Document 6 hereinafter, “Comparison of Contemporary CMOS Ring Oscillators” (IEEE RFICS. 2004, USA, June 2004, pp. 281 to 284) referred to as Non-Patent Document 7 hereinafter, “A Low Phase Noise 2.0V 900 MHz CMOS Voltage Controlled Ring Oscillator” (IEEE ISCAS. 2004, USA, May 2004, vol. 4, pp. 533 to 536) referred to as Non-Patent Document 8 hereinafter, and “A Low Voltage 900 MHz Voltage Controlled Ring Oscillator With Wide Tuning Range” (IEEE APCCAS. 2004, USA, December 2004, vol. 1, pp. 301 to 304) referred to as Non-Patent Document 9 hereinafter).